The present invention relates to a testing method of semiconductor memory devices such as an EEPROM (electrically erasable programmable ROM) and an EPROM (erasable programmable ROM).
In a conventional semiconductor manufacturing process, a group of packaged semiconductor memory devices are provided to a series of measurement steps to test their various electrical characteristics, in which the tests of the respective measurement steps are performed independently. For example, as shown in FIG. 4, a group of semiconductor memory devices is first input to measurement step 1, where their electrical characteristics (e.g., a response speed) under a high-temperature condition are evaluated to sort those devices. That is, in the measurement step 1, the semiconductor memory devices are sorted into, for instance, rank A, rank B and rank C in the order of superiority of the electrical characteristics. The semiconductor memory devices of ranks A-C are then input to respective measurement steps 2, where electrical characteristics under the normal temperature condition are evaluated to again sort the semiconductor memory devices into ranks A-C based on the evaluation results. The devices sorted in this manner are finally shipped.
However, this conventional testing method has the following problems.
As described above, the respective tests of the series of measurement steps are performed independently. Therefore, even if semiconductor devices of one measurement lot are erroneously input to the measurement step 2 skipping the measurement step 1, their electrical characteristics are tested in the measurement step 2 in the same manner as in the case of the normal flow. As a result, a semiconductor device that should be shipped as a rank C device because of its inferior electrical characteristics under the high-temperature condition may be shipped erroneously as a rank B device because of its average electrical characteristics under the normal temperature condition. Since an operation slip is attached to each group of semiconductor memory devices which is going through the measurement steps, an operator can find such erroneous skipping of some measurement step by checking the operation slip. However, even if a procedure is established in which operators are obliged to check the slips, there still exists a possibility that they inadvertently fail to find the erroneous skipping of an measurement step.
Further, in the conventional testing method, since a group of semiconductor memory devices is divided in the measurement step 1 into a plurality of groups, the number of groups (lots) going through the process are increased, so that the process management will become intricate as much.
Further, a handling machine (i.e., a measurement handler) for handling the semiconductor memory devices in the measurement step 1 needs to be equipped with is a sorting mechanism, which a factor of making the construction of the handling machine complex.